Generation of complex synthesized sounds such as speech requires some form of voice compression. One voice compression technique that has been heretofore utilized is linear predictive coding (LPC). LPC utilizes a digital lattice filter to model human speech from a set of prestored input parameters contained in a Read Only Memory (ROM). The LPC lattice filter typically is comprised of ten stages with each stage requiring two multiplications and two additions before passing the results backwards and forwards to its neighboring stages. The operations in the ten stages are carried out sequentially, as are the four operations within each stage. Processing of each prestored input parameter through the lattice filter results in a digital output value which is converted to an analog signal level and then amplified for output to a speaker or similar transducer.
In order to synthesize high quality speech with a digital lattice filter, it is necessary to process the prestored input parameters through the lattice filter at a repetition rate of approximately 10 kHz. To operate the lattice filter at this repetition rate, each stage must perform the digital operations therein within ten microseconds. The digital addition and/or subtraction operations required for each stage utilize a relatively straightforward process, whereas the digital multiplication operation is somewhat more complicated. Multiplication of two binary values requires iterative processing which may require up to four separate additions to yield a product, depending upon the length of the digital values multiplied. The processing of the two multiplications and two additions for each stage can therefore require the generation of up to ten separate sums.
Heretofore, the two multiplications and two additions for each stage have been performed in a parallel fashion with five sums being simultaneously generated in a pipeline fashion. In this manner, circuitry with a relatively slow response time can be utilized. However, to perform this parallel operation, five full adders are required resulting in a large parts count. This large parts count requires a significant amount of silicon surface area in order to realize the circuitry for the five full adders and the peripheral control circuitry necessary to support this number of full adders. From a cost and manufacturing standpoint, it would be desirable to utilize less circuitry to perform the same operation. Therefore, there exists a need for a circuit to process the multiplications and additions/subtractions required in each stage of the digital filter that is reliable and utilizes less circuitry without sacrificing processing time.